The present invention generally relates to a semiconductor integrated circuit device having an improved arrangement of power source lines. More particularly, the present invention is directed to an improvement in routing power source lines of a standard cell type LSI (large scale integrated circuit).
Power consumption of LSI chips is trending to an increase with an increase in integration density and speeding up operation. Particularly, fineness of wiring patterns deteriorates resistance to electromigration and shortens the lifetime of LSI chips. From these viewpoints, effective and efficient power supply is required to fabricate reliable LSI chips. Further, automatic routing of power source lines by use of computer aided design (CAD) is required to reduce the time it takes to design LSI chips.
FIG. 1 is a plan view of a conventional standard cell-type LSI chip. Referring to FIG. 1, the chip includes main (primary) power source lines 1-6, secondary or auxiliary power source lines 7-16, functional blocks (modules) 17-20, and an input/output (I/O) circuit block 21. The functional blocks 17-20 provide respective logics. For example, an arithmetic logic unit (ALU) is formed by a functional block. The functional block 19 includes unit cell arrays 22 each providing an NAND circuit, for example. The main power source lines 1-6 extend to the vicinity of the functional blocks 17-20 from power source terminals (not shown) provided in the I/O circuit block 21. The auxiliary power source lines 7-14 extend to the functional blocks 17-20 from the main power source lines 1-6 close thereto. In each of the functional blocks 17-20, the auxiliary power source lines 15 and 16 couple the unit cell arrays 22 and the auxiliary power source lines 7-14. An auxiliary power source line extending above the unit cell arrays 22 supplies each of the unit cell arrays 22 with power.
However, the conventional layout of power source lines shown in FIG. 1 presents the following disadvantages. First, it is very difficult to automatically route power source lines through CAD because there are no rules of routing the main power source lines 1-6 and additionally there are no rules of connection between the main power source lines 1-6 and the I/O circuit blocks 21. Second, an increased number of the main power source lines 1-6 or a thicker main power source lines 1-6 are necessary to supply the functional blocks 17-20 with sufficient power. The arrangement is not suitable for automatic routing power source lines. Third, even when sufficient power is supplied to the functional blocks 17-20, cells located in the center of each array or its vicinity are not supplied with sufficient power if the widths of the auxiliary power source lines are not enough to supply the unit cells with sufficient power.
An integrated circuit chip directed to an improvement in a layout of power source lines has been disclosed in Japanese Laid-Open Patent Application No. 59-207641. A mother power source line is arranged so as to surround the entire internal area in which a plurality of functional blocks are formed. Main power source lines extending in a first direction (lateral direction) are arranged so as to connect opposite portions of the mother power source line. Supporting power source lines extending on the opposite sides of each of the functional blocks are arranged in a second direction perpendicular to the first direction so as to connect the supporting power source lines or between the supporting power source lines and the mother power source line. Power source lines which provide unit cell arrays with power extend so as to connect the supporting power source lines arranged on both the sides of each functional block.
However, the unit cell arrays are supplied with power only through the power source lines provided so as to connect the supporting power source lines extending only in the second direction. Therefore, the degree of freedom to route power source lines is poor. In other words, the aforementioned arrangements of power source lines are not suitable for automatic design of routing through CAD. Further, for the same reason, it is very difficult to make the distribution of current uniform over the power source lines.